Many types of Analog-to-Digital Converters (ADC's) have been used for a wide variety of applications. Flash ADC's compare analog signal voltages to multiple voltage levels in an instant to produce a multi-bit digital word that represents the analog voltage. Successive-approximation ADC's use a series of stages to convert an analog voltage to digital bits. Each stage compares an analog voltage to a reference voltage, producing one digital bit. In sub-ranging ADC's, each stage compares an analog voltage to several voltage levels, so that each stage produces several bits. Succeeding stages generate lower-significant digital bits than do earlier stages in the pipeline.
Algorithmic, re-circulating, or recycling ADC's use a loop to convert an analog voltage. The analog voltage is sampled and compared to produce a most-significant digital bit. Then the digital bit is converted back to analog and subtracted from the analog voltage to produce a residue voltage. The residue voltage is then multiplied by two and looped back to the comparator to generate the next digital bit. Thus the digital bits are generated over multiple cycles in the same comparator stage.
FIG. 1 shows a Successive-Approximation-Register ADC. Successive-Approximation-Register SAR 302 receives a clock CLK and contains a register value that is changed to gradually zero-in on a close approximation of the analog input voltage VIN. For example, the value in SAR 302 may first be 0.5, then 0.25, then 0.32, then 0.28, then 0.30, then 0.31, then 0.315, then 0.313, then 0.312, when comparing to a VIN of 0.312 volts. SAR 302 outputs the current register value to digital-to-analog converter (DAC) 300, which receives a reference voltage VREF and converts the register value to an analog voltage VA.
The input analog voltage VIN is applied to sample-and-hold circuit 304, which samples and holds the value of VIN. For example, a capacitor can be charged by VIN and then the capacitor isolated from VIN to hold the analog voltage. The sampled input voltage from sample-and-hold circuit 304 is applied to the inverting input of comparator 306. The converted analog voltage VA is applied to the non-inverting input of comparator 306.
Comparator 306 compares the converted analog voltage VA to the sampled input voltage and generates a high output when the converted analog voltage VA is above the sampled VIN, and the register value in SAR 302 is too high. The register value in SAR 302 can then be reduced.
When the converted analog voltage VA is below the sampled input voltage, comparator 306 generates a low output to SAR 302. The register value in SAR 302 is too low. The register value in SAR 302 can then be increased for the next cycle.
The register value from SAR 302 is a binary value of N bits, with D(N−1) being the most-significant-bit (MSB) and D0 being the least-significant-bit (LSB). SAR 302 can first set the MSB D(N−1), then compare the converted analog voltage VA to the input voltage VIN, then adjust the MSB and/or set the next MSB D(N−2) based on the comparison. The set and compare cycle repeats until after N cycles the LSB is set. After the last cycle, the end-of-cycle EOC signal is activated to signal completion. A state machine or other controller can be used with or included inside SAR 302 to control sequencing.
Comparator 306 can be replaced with a series of pre-amplifier stages and a final latch. FIG. 2A is a response graph of pre-amplifier and latch stages. The pre-amplifier stages have a negative response shown by curve 312, while the final latch has a positive response as shown by curve 310. For low voltages, curve 312 is above and to the left curve 310, indicating that the pre-amplifiers require less time to achieve the same VOUT voltage than the latch. However, for higher VOUT voltages, curve 310 is above curve 312, indicating that for larger values of VOUT, the latch can achieve these larger voltage outputs much faster than the pre-amplifiers.
FIG. 2B shows a series of pre-amplifiers and a final latch. Pre-amplifier stages 320, 322, 324, 326, 328 are amplifiers that boost the voltage difference between VIN and VA. Especially near the end of comparison when the LSB is being set, the difference between VIN and VA can be quite small. This voltage difference is gradually increased by the pre-amplifier stages until the final stage. Latch stage 330 latches this voltage difference to generate the compare signal that is fed back to SAR 302. Thus stages 320-330 replace comparator 306 of FIG. 1.
By combining a series of pre-amplifier stages with the positive response of the final latch, a fast response time can be achieved. The pre-amplifier stages can gradually amplify and enlarge the voltage difference between VIN and VA until the amplified voltage difference is large enough to drive the final latch. The delay time can be minimized by using low-gain, wide bandwidth pre-amplifiers.
FIG. 3 shows a prior-art auto-zeroing amplifier stage for an ADC. Small mis-matches or other offset voltages in a comparator circuit can be larger than the voltage difference being compared. These offsets can be stored in the comparator during an auto-zeroing period and then cancelled during an amplifying period.
During the zeroing period, clock φ1 is active, closing switches 338, 346, 348, but φ2 is inactive, leaving switches 342, 344 open. The input voltages VIN+, VIN− are disconnected. Switch 346 equalizes the two inputs that receive VIN+, VIN− to the same voltage. Switch 338 connects the output of op amp 336 to its inverting input, providing a unity gain configuration. Offset voltage VOS 350 is a parasitic offset voltage rather than a voltage source such as a battery. When switch 338 is closed, and op amp 336 is in the unity gain configuration, VOS applied to the input of op amp 336 is driven to the output VOUT. Switch 348 also closes during φ1, driving the other end of VOS 350 to ground. Capacitor 340 isolates the negative terminal of VOS from the inputs. VOS is fed back from VOUT through switches 338, 348 to the other plate of capacitor 340, so VOS is effectively stored on capacitor 340 during the zeroing period.
During the amplifying period, φ1 is inactive and φ2 is active. Switches 338, 346, 348 open while switches 342, 344 close to connect VIN+, VIN− to the inputs of op amp 336. Capacitor 340 stored negative VOS during the zeroing period, so the VOS on capacitor 340 cancels VOS 350. The offset is canceled. VIN+ minus VOS plus VOS, or just VIN+, is applied to the non-inverting input of op amp 336. VIN− is applied to the inverting input of op amp 336, so op amp 336 amplifies the voltage difference VIN+, VIN− to generate VOUT.
A series of such stages can be cascaded together in a prior-art ADC. Offsets can be stored in each stage, and a final latch stage can stored the final amplified result. VIN+ to the first stage can be VA and VIN− can be VIN of FIG. 1.
Auto-zeroing requires a high-gain amplifier, yet a low-gain pre-amplifier was needed for high speed, such as shown in FIG. 2. This contradiction between high-gain and low-gain requirements makes design of such ADC's problematic. ADC's may have the desired gain, but may operate slowly or with fewer bits of precision. Tradeoffs may reduce the performance, either of speed or of precision, of the resulting ADC.
In critical comparisons, such as with many digital bits of precision, the voltage applied to the comparator is small enough such that all the outputs may end up in the linear input range; thus the time taken for each output to reach the linear input region is much greater. The overdrive recovery delay is roughly four times the delay of any one amplifier. The overdrive recovery delay is the time from when the input is first applied to the first preamplifier stage to the time when the output of the last preamplifier returns from saturation to linear operation. This increased overdrive recovery delay is undesirable. Extra amplifiers may be used to compensate, but these extra amplifiers increase cost and are also undesirable.
What is desired is a comparator stage for an ADC that can operate as both a low-gain preamplifier and a high-gain op amp. A stage that can provide unity-gain negative-feedback offset cancellation and low-gain pre-amplification is desired. A dual-use stage in an ADC is desirable.